A unified design space for regular parallel prefix adders-Reference-Cited by-同舟云学术

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A unified design space for regular parallel prefix adders

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Container-title:Proceedings Design, Automation and Test in Europe Conference and Exhibition
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Author:

Ziegler M.M.,Stan M.R.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/8959/28391/01269100.pdf?arnumber=1269100

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Power reduction and speed improvement of high-speed adder using Han-Carlson Adder in comparison with the Ladner Fischer Adder;AIP Conference Proceedings;2024

2. Power reduction and speed improvement of high-speed adder using Han-Carlson Adder in comparison with the Ladner Fischer Adder;AIP Conference Proceedings;2024

3. Design of In-Memory Parallel-Prefix Adders;Journal of Low Power Electronics and Applications;2021-11-24

4. A Ling-Enhanced Adder for IEEE-compliant Floating-Point Multiplication;2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS);2020-08

5. A Number System Approach for Adder Topologies;2017 IEEE 24th Symposium on Computer Arithmetic (ARITH);2017-07

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