Author:
Keezer D.C.,Minier D.,Ducharme P.
Cited by
5 articles.
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1. Multi-Stage Jitter-Reduction and Frequency Multiplication for 54 GHz ATE Clocks;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18
2. Characterization of Ultra-low Random Jitter Reduction Methods up to 36 GHz;2024 IEEE European Test Symposium (ETS);2024-05-20
3. Jitter Reduction for Multi-GHZ ATE Up to 20 GHZ;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17
4. Experimental Evaluation of Jitter Reduction Methods for Multi-Gigahertz Test;2023 IEEE International Test Conference in Asia (ITC-Asia);2023-09-12
5. Transmitter Jitter Extractions on ATE;Accelerating Test, Validation and Debug of High Speed Serial Interfaces;2010-10-11