A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/9609/30361/01395520.pdf?arnumber=1395520
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design and analysis of the Chameleon scheduling algorithm for reconfigurable computing;2022 2nd International Conference on Technological Advancements in Computational Sciences (ICTACS);2022-10-10
2. Optimizing GPU Register Usage: Extensions to OpenACC and Compiler Optimizations;2016 45th International Conference on Parallel Processing (ICPP);2016-08
3. Design of Image Processing Embedded Systems Using Multidimensional Data Flow;EMBED SYST;2011
4. Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization;The Computer Journal;2009-04-08
5. Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2009-03
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