Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework

Author:

Qiang Liu ,Constantinides G.A.,Masselos K.,Cheung P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Model-Platform Optimized Deep Neural Network Accelerator Generation through Mixed-Integer Geometric Programming;2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2023-05

2. FPGA Memory Optimization in High-Level Synthesis;Advances in Systems Analysis, Software Engineering, and High Performance Computing;2020

3. Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-08

4. Custom Multicache Architectures for Heap Manipulating Programs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017-05

5. An efficient and compact row buffer architecture on FPGA for real-time neighbourhood image processing;Journal of Real-Time Image Processing;2017-04-24

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