A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms-Reference-Cited by-同舟云学术

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A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms

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Container-title:Design, Automation and Test in Europe
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Author:

Kempf T.,Doerper M.,Leupers R.,Ascheid G.,Meyr H.,Kogel T.,Vanthournout B.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/9609/30361/01395693.pdf?arnumber=1395693

Cited by 31 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel Network On Chip Architecture For FPGA Smart NIC;2023 IEEE Women in Technology Conference (WINTECHCON);2023-09-21

2. Optimizing High Bandwidth Memory in Multi-Die Systems;2023 IEEE Women in Technology Conference (WINTECHCON);2023-09-21

3. Narrowing the Search Space of Applications Mapping on Hierarchical Topologies;2021 International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS);2021-11

4. Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements;ACM Transactions on Design Automation of Electronic Systems;2021-05-31

5. Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization;ACM Transactions on Design Automation of Electronic Systems;2019-06

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