Non-Volatile Latch Compatible With Static and Dynamic CMOS for Logic in Memory Applications
Author:
Affiliation:
1. Department of Electronics Engineering, Indian Institute of Technology (BHU) Varanasi, Varanasi, India
Funder
Science and Engineering Board (SERB) and Seed Grant of IIT BHU
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/20/9737705/09706462.pdf?arnumber=9706462
Reference33 articles.
1. Variation-Resilient True Random Number Generators Based on Multiple STT-MTJs
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4. Evaluation of a non-volatile FPGA based on MRAM technology;zhao;Proc IEEE Int Conf IC Design Technol,2006
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