Innovative Circuit Board Level Routing Designs for BGA Packages
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/6040/29777/01356005.pdf?arnumber=1356005
Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Fast Escape Router for Large-Scale Staggered-Pin-Array PCBs;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08
2. Y-architecture-based flip-chip routing with dynamic programming-based bend minimization;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10
3. Localized Multi-axis Loading Impact on Interconnect Thermal Cycling Performance in Via-in-Pad Plated Over (VIPPO) Board Configuration;Journal of Electronic Materials;2020-08-27
4. Escape Routing for Staggered-Pin-Array PCBs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2013-09
5. Study of Signal Transmission for SIP and POP;Applied Mechanics and Materials;2012-11
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