Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning*
Author:
Affiliation:
1. Duke University,Department of Electrical & Computer Engineering,USA
2. Arizona State University,School of Electrical, Computer and Energy Engineering,USA
Funder
National Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10173930/10173940/10174135.pdf?arnumber=10174135
Reference19 articles.
1. RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning
2. Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
3. Survey of low-power testing of VLSI circuits
4. TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs
5. A graph placement methodology for fast chip design
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Testing and Fault Diagnosis for Multi-level Resistive Random-Access Memory in Monolithic 3D Integration*;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22
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