RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/9585997/9586083/09586138.pdf?arnumber=9586138
Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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2. RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09
3. AGD: A Learning-based Optimization Framework for EDA and its Application to Gate Sizing;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09
4. Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning*;2023 IEEE European Test Symposium (ETS);2023-05-22
5. RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04
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