Accelerating SpMV on FPGAs by Compressing Nonzero Values-Reference-Cited by-同舟云学术

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Accelerating SpMV on FPGAs by Compressing Nonzero Values

Published:2015-05 Issue: Volume: Page:
ISSN:
Container-title:2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines
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Author:

Grigoras Paul,Burovskiy Pavel,Hung Eddie,Luk Wayne

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7155747/7160017/07160041.pdf?arnumber=7160041

Cited by 32 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. SPADES: A 0.54-GFLOPS/W Sparse Matrix Vector Multiplication Accelerator Featuring On-the-Fly GZIP Decompression for 3.36X Reduction in Off-Chip Data Movement;Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design;2024-08-05

2. HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAs;Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2024-04

3. Open-Source SpMV Multiplication Hardware Accelerator for FPGA-Based HPC Systems;Lecture Notes in Computer Science;2024

4. Adaptive Lossy Data Compression Extended Architecture for Memory Bandwidth Conservation in SpMV;IEICE Transactions on Information and Systems;2023-12-01

5. Feature-based SpMV Performance Analysis on Contemporary Devices;2023 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2023-05

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