SPADES: A 0.54-GFLOPS/W Sparse Matrix Vector Multiplication Accelerator Featuring On-the-Fly GZIP Decompression for 3.36X Reduction in Off-Chip Data Movement-Reference-Cited by-同舟云学术

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SPADES: A 0.54-GFLOPS/W Sparse Matrix Vector Multiplication Accelerator Featuring On-the-Fly GZIP Decompression for 3.36X Reduction in Off-Chip Data Movement

Published:2024-08-05 Issue: Volume: Page:1-6
ISSN:
Container-title:Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design
language:
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Author:

Huang Paul Xuanyuanliang¹^ORCID,Tsividis Yannis¹^ORCID,Seok Mingoo¹^ORCID

Affiliation:

1. Columbia University, New York, NY, United States

Funder

NSF (National Science Foundation)

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3665314.3670811

Reference10 articles.

1. Data Compression Accelerator on IBM POWER9 and z15 Processors : Industrial Product

2. ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator

3. The university of Florida sparse matrix collection

4. A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoT

5. Accelerating SpMV on FPGAs by Compressing Nonzero Values

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