Very low bandgap voltage reference with high PSRR enhancement stage implemented in 90nm CMOS process technology for LDO application-Reference-Cited by-同舟云学术

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Very low bandgap voltage reference with high PSRR enhancement stage implemented in 90nm CMOS process technology for LDO application

Published:2012-11 Issue: Volume: Page:
ISSN:
Container-title:2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)
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Author:

Francisco Keith R.,Hora Jefferson A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6504611/6507766/06507800.pdf?arnumber=6507800

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 22nm FDSOI Forward Body Biasing in Designing Ultra-Low Power, High PSRR Voltage Reference for IoT Power Management Applications;TENCON 2023 - 2023 IEEE Region 10 Conference (TENCON);2023-10-31

2. A Comprehensive Study of Different Techniques for Voltage References;Journal of Circuits, Systems and Computers;2023-05-29

3. Design Methodology of a Voltage Bandgap Reference with High PSRR in Advanced Technology Nodes for LDO Application;2022 IEEE 14th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment, and Management (HNICEM);2022-12-01

4. A Nano-Watt, Subthreshold Self-Biased CMOS Voltage Reference without Resistors and BJT;TENCON 2022 - 2022 IEEE Region 10 Conference (TENCON);2022-11-01

5. Process Corner Analysis for Recyclic Folded Cascode Operational Amplifiers at 180 nm SCL Technology;Lecture Notes in Electrical Engineering;2022-07-12

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