Design Methodology of a Voltage Bandgap Reference with High PSRR in Advanced Technology Nodes for LDO Application
Author:
Affiliation:
1. Mindanao State University - Iligan Institute of Tecnhnology,Microelelctronics Laboratory,Iligan City,Philippines
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10109352/10109274/10109433.pdf?arnumber=10109433
Reference17 articles.
1. Analysis and design of a current-mode bandgap reference with high power supply ripple rejection
2. Very low bandgap voltage reference with high PSRR enhancement stage implemented in 90nm CMOS process technology for LDO application
3. Design considerations of recent advanced low-voltage low-temperature-coefficient CMOS bandgap voltage reference
4. CMOS 1.2V bandgap voltage reference design
5. Design and characterization of bandgap voltage reference
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1. Design of Bandgap Voltage Reference Circuit with High-PSR and High-Accuracy;2023 3rd International Conference on Electronic Information Engineering and Computer Communication (EIECC);2023-12-22
2. 22nm FDSOI Forward Body Biasing in Designing Ultra-Low Power, High PSRR Voltage Reference for IoT Power Management Applications;TENCON 2023 - 2023 IEEE Region 10 Conference (TENCON);2023-10-31
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