A new design of XOR-XNOR gates for low power application
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5949580/5959023/05959039.pdf?arnumber=5959039
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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5. Optimising nanometric CMOS logic cells for low-power, low-energy, and noise margin;International Journal of Electronics;2017-02-16
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