Performance trade-offs for microprocessor cache memories-Reference-Cited by-同舟云学术

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Performance trade-offs for microprocessor cache memories

Published:1988-08 Issue:4 Volume:8 Page:44-54
ISSN:0272-1732
Container-title:IEEE Micro
language:
Short-container-title:IEEE Micro

Author:

Alpert D.B.,Flynn M.J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx1/40/409/00007771.pdf?arnumber=7771

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture;ACM Transactions on Architecture and Code Optimization;2024-09-14

2. High-Performance Memory Systems;The Microarchitecture of Pipelined and Superscalar Computers;1999

3. On use of fuzzy logic technology in operating systems;Fuzzy Sets and Systems;1998-11

4. Optimal allocation of on-chip memory for multiple-API operating systems;ACM SIGARCH Computer Architecture News;1994-04

5. A unified architectural tradeoff methodology;ACM SIGARCH Computer Architecture News;1994-04

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