Novel CMOS static ternary logic using double pass-transistor logic-Reference-Cited by-同舟云学术

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Novel CMOS static ternary logic using double pass-transistor logic

Published:2010-12 Issue: Volume: Page:
ISSN:
Container-title:The 2nd International Conference on Information Science and Engineering
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Author:

Hang Guoqiang,Xuanchang Zhou

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5680733/5688492/05689867.pdf?arnumber=5689867

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. DPL-based novel CMOS 1-Trit Ternary Full-Adder;International Journal of Electronics;2020-07-09

2. DPL-Based Novel 1-Trit Ternary Half-Subtractor;Lecture Notes in Electrical Engineering;2019-12-17

3. DPL-based novel Binary-to-ternary converter on CMOS technology;AEU - International Journal of Electronics and Communications;2018-08

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