DPL-based novel Binary-to-ternary converter on CMOS technology

Author:

Saha Aloke,Pal DipankarORCID

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology;Physica Scripta;2024-07-22

2. Power Efficient Novel CMOS Double-base to Binary Encoder (DBE);2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S);2024-06-08

3. Energy-Efficient Ternary Modulator for Wireless Sensor Networks;JOURNAL OF SENSOR SCIENCE AND TECHNOLOGY;2024-05-31

4. Performance Evaluation of Novel Ternary Subtractor Circuits using Double Pass Transistor Logic;2023 4th IEEE Global Conference for Advancement in Technology (GCAT);2023-10-06

5. Novel Single-Step 32nm-CMOS Hardware T-Encryptor/Decryptor;IETE Journal of Research;2023-04-25

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