A method of fault analysis for test generation and fault diagnosis-Reference-Cited by-同舟云学术

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A method of fault analysis for test generation and fault diagnosis

Published:1988-07 Issue:7 Volume:7 Page:813-833
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Cox H.,Rajski J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx1/43/222/00003952.pdf?arnumber=3952

Cited by 54 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Diagnosis of Double Faults Consisting of a Stuck-at Fault and a Transition Fault;2024 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC);2024-07-02

2. Logic Fault Diagnosis of Hidden Delay Defects;2020 IEEE International Test Conference (ITC);2020-11-01

3. An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-10

4. An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults;IEEE Transactions on Circuits and Systems I: Regular Papers;2018-03

5. Test digitaler Schaltkreise;2014-12-31

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