Low delta-I noise CMOS circuits based on differential logic and current limiters-Reference-Cited by-同舟云学术

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Low delta-I noise CMOS circuits based on differential logic and current limiters

Published:1999-07 Issue:7 Volume:46 Page:872-876
ISSN:1057-7122
Container-title:IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Gonzalez J.L.,Rubio A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/81/16802/00774239.pdf?arnumber=774239

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment;Proceedings of the Great Lakes Symposium on VLSI 2022;2022-06-06

2. CMOS Current-Mode Circuits for Data Communications;Analog Circuits and Signal Processing;2007

3. Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level;Lecture Notes in Computer Science;2002

4. Techniques for Avoiding Interconnection Noise;Interconnection Noise in VLSI Circuits

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