Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism-Reference-Cited by-同舟云学术

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Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism

Published:2014-01 Issue: Volume: Page:
ISSN:
Container-title:2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems
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Author:

Haghbayan M.H.,Alizadeh B.,Behnam P.,Safari S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6732243/6733066/06733110.pdf?arnumber=6733110

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Formal Verification of Integer Dividers:Division by a Constant;2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2019-07

2. Formal Verification of Approximate Sequential Circuits;Design Automation Techniques for Approximation Circuits;2018-10-10

3. Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis Reduction;2017 IEEE International Conference on Computer Design (ICCD);2017-11

4. Precise error determination of approximated components in sequential circuits with model checking;Proceedings of the 53rd Annual Design Automation Conference;2016-06-05

5. A dynamic specification to automatically debug and correct various divider circuits;Integration;2016-03

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