A 237–263 GHz CMOS Frequency Doubler with 0.9 dBm Output Power and 2.87 % Power Efficiency Based on Harmonic Matched $G_{\max}$-Core
Author:
Affiliation:
1. KAIST,Department of Electrical Engineering,Republic of Korea
Funder
Institute of Information & communications Technology Planning & Evaluation (IITP)
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9865233/9865240/09865611.pdf?arnumber=9865611
Reference9 articles.
1. A 213-233 GHz ×9 Frequency Multiplier Chain with 4.1 dBm Output Power in 40nm Bulk CMOS
2. A +3.0-dBm 115–129-GHz CMOS Power-Efficient Injection-Locked Frequency Tripler Chain
3. A CMOS High-Power Broadband 260-GHz Radiator Array for Spectroscopy
4. Single-ended HEMT multiplier design using reflector networks
5. A Wideband SiGe BiCMOS Frequency Doubler With 6.5-dBm Peak Output Power for Millimeter-Wave Signal Sources
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1. A Compact 24.5–32.6 GHz CMOS Frequency Doubler Based on Coupled Inductor;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-05
2. 185–215 GHz CMOS Frequency Doubler with a Single Row Staggered Distribution Layout Design;Electronics;2023-08-05
3. 24.2 A 264-to-287GHz, −2.5dBm Output Power, and −92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19
4. Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques;IEEE Access;2023
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