Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits-Reference-Cited by-同舟云学术

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Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits

Published:2011-05 Issue: Volume: Page:
ISSN:
Container-title:2011 Sixteenth IEEE European Test Symposium
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Author:

Raik Jaan,Rannaste Anna,Jenihhin Maksim,Viilukas Taavi,Ubar Raimund,Fujiwara Hideo

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5955410/5957904/05957938.pdf?arnumber=5957938

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations;Journal of Electronic Testing;2019-11-13

2. New categories of Safe Faults in a processor-based Embedded System;2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS);2019-04

3. UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs;Integration;2016-09

4. Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints;Journal of Electronic Testing;2012-07-13

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