Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4274802/4274803/04274829.pdf?arnumber=4274829
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. On the Susceptibility of QDI Circuits to Transient Faults;Lecture Notes in Computer Science;2023
2. Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines;2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS);2021-04-07
3. Identification and Confinement of Fault Sensitivity Windows in QDI Logic;2020 Austrochip Workshop on Microelectronics (Austrochip);2020-10-07
4. An infrastructure for accurate characterization of single-event transients in digital circuits;Microprocessors and Microsystems;2013-11
5. Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects;2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems;2012-05
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