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Springer Nature Switzerland
Reference13 articles.
1. Martin, A.J.: Compiling communicating processes into delay-insensitive VLSI circuits. Distrib. Comput. 1(4), 226–234 (1986)
2. Bainbridge, W.J., Salisbury, S.J.: Glitch sensitivity and defense of quasi delay-insensitive network-on-chip links. In: 2009 15th IEEE Symposium on Asynchronous Circuits and Systems, pp. 35–44. IEEE (2009)
3. LaFrieda, C., Manohar, R.: Fault detection and isolation techniques for quasi delay-insensitive circuits. In: International Conference on Dependable Systems and Networks, pp. 41–50. IEEE (2004)
4. Peng, S., Manohar, R.: Efficient failure detection in pipelined asynchronous circuits. In: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2005), pp. 484–493. IEEE (2005)
5. Monnet, Y., Renaudin, M., Leveugle, R.: Formal analysis of quasi delay insensitive circuits behavior in the presence of SEUs. In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), pp. 113–120. IEEE (2007)