On transistor level gate sizing for increased robustness to transient faults-Reference-Cited by-同舟云学术

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On transistor level gate sizing for increased robustness to transient faults

Published:2005 Issue: Volume: Page:
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Container-title:11th IEEE International On-Line Testing Symposium
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Author:

Cazeaux J.M.,Rossi D.,Omana M.,Metra C.,Chatterjee A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/10031/32176/01498124.pdf?arnumber=1498124

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