A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture-Reference-Cited by-同舟云学术

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A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

Published:1991 Issue:11 Volume:26 Page:1577-1585
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Chappell T.I.,Chappell B.A.,Schuster S.E.,Allan J.W.,Klepner S.P.,Joshi R.V.,Franch R.L.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx1/4/3123/00098975.pdf?arnumber=98975

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