A power-performance tunable logic with adjustable threshold pseudo-dynamic building blocks and CMOS compatibility

Author:

Ghaffarishad Hanieh1,Mohammadzadeh Naser1ORCID,Ghaznavi-Ghoushchi Mohammad-Bagher1

Affiliation:

1. Department of Electrical and Computer Engineering; Shahed University; Tehran Iran

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference47 articles.

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2. Chang K-J Accurate on-chip variation modeling to achieve design for manufacturability System-on-Chip for Real-Time Applications, 2004. Proceedings. 4th IEEE International Workshop on 2004 219 222

3. Kao J Narendra S Chandrakasan A Subthreshold leakage modeling and reduction techniques Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design 2002 141 148

4. Adaptive body bias for reducing the impacts of NBTI and process variations on 6T SRAM cells;Mostafa;IEEE Transactions on Circuits and Systems I: Regular Papers,2011

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