Ideal Behavior of Vernier and Flash TDCs Implemented in a Spartan-6 FPGA-Reference-Cited by-同舟云学术

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Ideal Behavior of Vernier and Flash TDCs Implemented in a Spartan-6 FPGA

Published:2023-03-06 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference on Advances in Electronics, Control and Communication Systems (ICAECCS)
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Author:

Chouial Wafia¹,Maamoun Mountassar¹

Affiliation:

1. Signal Processing and Image Laboratory University of Blida 1,Blida,Algeria

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10104518/10104524/10104626.pdf?arnumber=10104626

Reference14 articles.

1. Time-to-Digital Converters

2. A 1.7 ps Equivalent Bin Size and 4.2 ps RMS FPGA TDC Based on Multichain Measurements Averaging Method

3. Analysis and Correction of Noise Injection Due to Parallel-Output-Misalignment (POM) Effects in Ring-Type Time-to-Digital Converters (TDCs)

4. Time-to-Digital Converter Using a Tuned-Delay Line Evaluated in 28-, 40-, and 45-nm FPGAs

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