Time-to-Digital Converter Using a Tuned-Delay Line Evaluated in 28-, 40-, and 45-nm FPGAs-Reference-Cited by-同舟云学术

Time-to-Digital Converter Using a Tuned-Delay Line Evaluated in 28-, 40-, and 45-nm FPGAs

Published:2016-07 Issue:7 Volume:65 Page:1678-1689
ISSN:0018-9456
Container-title:IEEE Transactions on Instrumentation and Measurement
language:
Short-container-title:IEEE Trans. Instrum. Meas.

Author:

Won Jun Yeon,Lee Jae Sung

Funder

National Research Foundation of Korea within the Ministry of Science, ICT and Future Planning through the Korean Government

Korea Health Industry Development Institute within the Ministry of Health and Welfare through the Korea Health Technology Research and Development Project, Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Instrumentation

Link

http://xplorestaging.ieee.org/ielx7/19/7486162/07448918.pdf?arnumber=7448918

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