Statistical timing optimization of combinational logic circuits-Reference-Cited by-同舟云学术

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Statistical timing optimization of combinational logic circuits

Published: Issue: Volume: Page:
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Container-title:Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93
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Author:

Jyu H.-F.,Malik S.

Publisher

IEEE Comput. Soc. Press

Link

http://xplorestaging.ieee.org/ielx2/3140/8949/00393401.pdf?arnumber=393401

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Artificial neural network model for arrival time computation in gate level circuits;Automatika;2019-07-03

2. Managing contamination delay to improve Timing Speculation architectures;PeerJ Computer Science;2016-08-22

3. Voltage scheduling under unpredictabilities: a risk management paradigm;ACM Transactions on Design Automation of Electronic Systems;2005-04

4. A modular neural network approach to microelectronic circuit yield optimization;Microelectronics Reliability;1998-04

5. Statistical performance-driven module binding in high-level synthesis;Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210)

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