Semiconductor Architectures Enable Compute in Memory
Author:
Affiliation:
1. Objective Analysis, Los Gatos, USA
2. Coughlin Associates, Inc., San Jose, USA
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Computer Science
Link
http://xplorestaging.ieee.org/ielx7/2/10109259/10109294.pdf?arnumber=10109294
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4. A nonvolatile AI-edge processor with 4MB SLC-MLC hybrid-mode ReRAM compute-in-memory macro and 51.4-251TOPS/W;huang;Int Solid-State Circuits Conf,0
5. 16.4 TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration
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1. A Performance-driven Neural Network Compiler for Multi-core Computing-In-Memory Accelerator;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
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