Voltage and temperature dependence of random telegraph noise in highly scaled HKMG ETSOI nFETs and its impact on logic delay uncertainty

Author:

Miki H.,Yamaoka M.,Frank D. J.,Cheng K.,Park D.-G.,Leobandung E.,Torii K.

Publisher

IEEE

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A New Method of Automatic Extraction of RTN and OMI-Friendly Implementation;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14

2. Random Telegraph Noise and Bias Temperature Instabilities statistical characterization of Ω-gate FDSOI devices at low voltages;Solid-State Electronics;2023-11

3. Random Telegraph Noise Simulation and the Impact on Noise Sensitive Design;2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD);2023-09-27

4. Mechanism of Random Telegraph Noise in 22-nm FDSOI-Based MOSFET at Cryogenic Temperatures;Nanomaterials;2022-12-06

5. A fast and test-proven methodology of assessing RTN/fluctuation on deeply scaled nano pMOSFETs;2020 IEEE International Reliability Physics Symposium (IRPS);2020-04

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