III–V and Ge/strained SOI tunneling FET technologies for low power LSIs
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7198535/7223619/07223687.pdf?arnumber=7223687
Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Study of scaling effect of ferroelectric gate stack in planar InGaAs MOSFET;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2022-08-19
2. Performance Evaluation of Double-Gate Tunnel Field-Effect Transistor with Germanium Epitaxial Layer;Lecture Notes in Electrical Engineering;2021-09-10
3. Advanced CMOS technologies for ultra-low power logic and AI applications;2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2021-04-08
4. Optimization of spacer and source/channel junction to improve TFET characteristics;IEICE Electronics Express;2020-09-10
5. Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure;Applied Sciences;2020-08-04
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