Optimization of spacer and source/channel junction to improve TFET characteristics-Reference-Cited by-同舟云学术

Optimization of spacer and source/channel junction to improve TFET characteristics

Published:2020-09-10 Issue:17 Volume:17 Page:20200211-20200211
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Kim Garam¹,Kim JangHyun²,Kim Sangwan³

Affiliation:

1. Dept. of Electronic Engineering, Myongji University

2. School of Electrical Engineering, Pukyong National University

3. Dept. of Electrical and Computer Engineering, Ajou University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/17/17/17_17.20200211/_pdf

Reference31 articles.

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2. [2] D.J. Frank, et al.: “Device scaling limits of Si MOSFETs and their application dependencies,” Proc. IEEE 89 (2001) 259 (DOI: 10.1109/5.915374).

3. [3] A. Padilla, et al.: “Feedback FET: a novel transistor exhibiting steep switching behavior at low bias voltages,” IEEE International Electron Devices Meeting (2008) 1 (DOI: 10.1109/IEDM.2008.4796643).

4. [4] S. Hwang, et al.: “Si_1-xGe_x positive feedback field-effect transistor with steep subthreshold swing for low-voltage operation,” J. Semicond. Technol. Sci. 17 (2017) 216 (DOI: 10.5573/JSTS.2017.17.2.216).

5. [5] K.-S. Li, et al.: “Sub-60mV-swing negative-capacitance FinFET without hysteresis,” IEEE International Electron Devices Meeting (2015) 22 (DOI: 10.1109/IEDM.2015.7409760).

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