Band-Engineered Low PMOS V<inf>T</inf> with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme-Reference-Cited by-同舟云学术

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Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

Published:2007-06 Issue: Volume: Page:
ISSN:
Container-title:2007 IEEE Symposium on VLSI Technology
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Author:

Harris H. Rusty,Kalra Pankaj,Majhi Prashant,Hussain Muhammed,Kelly David,Oh Jungwoo,He Dawei,Smith Casey,Barnett Joel,Kirsch Paul D.,Gebara Gabriel,Jur Jess,Lichtenwalner Daniel,Lubow Abigail,Ma T.P.,Sung Guangyu,Thompson Scott,Lee Byoung Hun,Tseng Hsing-Huang,Jammy Raj

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4339664/4339665/04339763.pdf?arnumber=4339763

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