A high-density logic CMOS process compatible non-volatile memory for sub-28nm technologies-Reference-Cited by-同舟云学术

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A high-density logic CMOS process compatible non-volatile memory for sub-28nm technologies

Published:2014-06 Issue: Volume: Page:
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Container-title:2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers
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Author:

Shen Rick Shih-Jye,Wu Meng-Yi,Chen Hsin-Ming,Lu Chris Chun-Hung

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6886509/6894335/06894353.pdf?arnumber=6894353

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor;IPSJ Transactions on System and LSI Design Methodology;2023

3. Antifuse OTP Cell in a Cross-Point Array by Advanced CMOS FinFET Process;IEEE Transactions on Electron Devices;2019-04

4. One Time Programmable Antifuse Memory Based on Bulk Junctionless Transistor;IEEE Electron Device Letters;2018-08

5. P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors;Japanese Journal of Applied Physics;2018-03-22

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