A Synthesis Method for Verilog Case Statement Using Mux-and-Inverter Graph
Author:
Affiliation:
1. Beijing Microelectronics Technology Institute,Beijing,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10218344/10218369/10218672.pdf?arnumber=10218672
Reference10 articles.
1. Delay minimal decomposition of multiplexers in technology mapping;thakur;Proc 33rd Design Automation Conf,0
2. DESIGN OF TREE-TYPE LOGIC NETWORKS USING MULTIPLEXERS;jiang;Journal of electronics information technology,1992
3. Efficient multiplexer synthesis techniques
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1. Network-Architecture-Aware Multiplexer Decomposition for Technology Mapping;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09
2. A novel approach to the fabrication of photonic XOR and XNOR gates employing a 2:1 all-optical multiplexer made of nonlinear Kerr type materials;Proceedings of the Indian National Science Academy;2024-03-08
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