Network-Architecture-Aware Multiplexer Decomposition for Technology Mapping-Reference-Cited by-同舟云学术

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Network-Architecture-Aware Multiplexer Decomposition for Technology Mapping

Published:2024-09 Issue:9 Volume:71 Page:4201-4205
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Chen Yilu¹^ORCID,Lin Zhifeng¹^ORCID,Liang Xiaojian²,Cai Zhijie³,Bai Xiqiong⁴,Chen Jianli³^ORCID

Affiliation:

1. Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou, China

2. College of Computer and Data Science, Fuzhou University, Fuzhou, China

3. School of Microelectronics, Fudan University, Shanghai, China

4. School of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing, China

Funder

National Natural Science Foundation of China

National Key Research and Development Program of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8920/10666887/10504889.pdf?arnumber=10504889

Reference21 articles.

1. Logic Synthesis

2. Delay minimal decomposition of multiplexers in technology mapping

3. Combinational logic synthesis for LUT based field programmable gate arrays

4. A Novel Multiplexer-Based Low-Power Full Adder

5. Design and implementation of Carry Select Adder without using multiplexers

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