An efficient analysis for True Random number generators using A Postprocessor, Jitter Metastability, Tree-Based Interleaver & CMOS inverter prototype technology
Author:
Affiliation:
1. HBTU,Electronics Engineering Department,Kanpur,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10026847/10026888/10027075.pdf?arnumber=10027075
Reference12 articles.
1. Design and validation of high speed true random number generators based on prime-length ring oscillators
2. A Highly Flexible Lightweight and High Speed True Random Number Generator on FPGA
3. A Hybrid True Random Number Generator using Ring Oscillator and Digital Clock Manager
4. FPGA implementation of random number generator using LFSR and scrambling algorithm for lightweight cryptography
5. A True Random Number Generator with Time Multiplexed Sources of Randomness
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