Co-packaging of PMUT array with FOWLP ASIC's-Reference-Cited by-同舟云学术

Co-packaging of PMUT array with FOWLP ASIC's

Published:2022-12-07 Issue: Volume: Page:
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Container-title:2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)
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Author:

Giusti Domenico¹,Quaglia Fabio¹,Rahul Dutta²,Rao Vempati Srinivasa²,Savoia Alessandro³,Shaw Mark¹,Wee David Ho Soon²

Affiliation:

1. ST Microelectronics Agrate,Agrate Brianza,Italy,20864

2. Institute of Microelectronics,Singapore,138635

3. Roma Tre University,Rome,Italy

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10012686/10013085/10013202.pdf?arnumber=10013202

Reference5 articles.

1. A 3D packaging technology for acoustically optimized integration of 2D CMUT arrays and front end circuits;savoia;Proceedings IEEE International Ultrasonics Symposium,2017

2. Back Cavity Formation on 50um Thick bumped PMUT wafers;giusti;Proc EPTC,2022

3. cMUT sensor for applications as a wide-band acoustic receiver in the MHz range

4. Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications

5. Ultrasound-on-chip platform for medical imaging, analysis, and collective intelligence

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