Wafer Warpage Optimization Via Finite Element Analysis for a 3D Chiplet Package
Author:
Affiliation:
1. Institute of Microelectronics, A*STAR (Agency for Science, Technology, and Research),Singapore,138634
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10012686/10013085/10013285.pdf?arnumber=10013285
Reference4 articles.
1. Dynamic Mechanical Analysis and Viscoelastic Behavior of Epoxy Molding Compounds Used in Fan-Out Wafer-Level Packaging
2. Numerical study on wafer level warpage evolution during chip to wafer hybrid bonding process
3. Modelling and characterization on wafer to wafer hybrid bonding technology for 3D IC packaging
4. Development of Wafer-Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV Wafers
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1. Optimization design and experimental verification of a high-precision wafer carrier with high and low temperatures;Fourth International Conference on Mechanical Engineering, Intelligent Manufacturing, and Automation Technology (MEMAT 2023);2024-04-01
2. Identify critical packaging parameters impacting wafer warpage using FEA and statistical analysis techniques;2023 IEEE 25th Electronics Packaging Technology Conference (EPTC);2023-12-05
3. Board level FEA reliability and stress modeling for chip-to-wafer bonded chiplet package;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05
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