DFT Computation Using Gauss-Eisenstein Basis: FFT Algorithms and VLSI Architectures-Reference-Cited by-同舟云学术

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DFT Computation Using Gauss-Eisenstein Basis: FFT Algorithms and VLSI Architectures

Published:2017-08-01 Issue:8 Volume:66 Page:1442-1448
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Coelho Diego F. G.,Cintra Renato J.,Rajapaksha Nilanka,Mendis Gihan J.,Madanayake Arjuna,Dimitrov Vassil S.

Funder

CNPq

FACEPE

NSERC

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx7/12/7972690/07869325.pdf?arnumber=7869325

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Designing 64-Bit LUT based FFT Structure for High-Speed DSP Applications;2023 IEEE 12th International Conference on Communication Systems and Network Technologies (CSNT);2023-04-08

2. Efficient pipelined FFT hardware design for IEEE 754 single precision computing;Journal of Information and Optimization Sciences;2022-04-03

3. An area efficient FFT and its hardware implementation;Journal of Information and Optimization Sciences;2022-04-03

4. Field Programmable Gate Arrays (FPGA) Based Computational Complexity Analysis of Multicarrier Waveforms;Intelligent Automation & Soft Computing;2022

5. A study on VLSI implementation of image enhancement techniques;Concurrency and Computation: Practice and Experience;2021-11-29

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