Efficient pipelined FFT hardware design for IEEE 754 single precision computing-Reference-Cited by-同舟云学术

Efficient pipelined FFT hardware design for IEEE 754 single precision computing

Published:2022-04-03 Issue:3 Volume:43 Page:629-634
ISSN:0252-2667
Container-title:Journal of Information and Optimization Sciences
language:en
Short-container-title:Journal of Information and Optimization Sciences

Author:

Sharma Manoj¹,Kumar Shivam¹,Priyadarshi Prakhar²,Goyal Vishal³

Affiliation:

1. Department of Electronics and Communication Engineering, Bharati Vidyapeeth’s College of Engineering, New Delhi 110064 India

2. Department of Information Technology, Bharati Vidyapeeth’s College of Engineering, New Delhi 110064, India

3. Department of Electronics and Communications Engineering, GLA University, Mathura, UP, India

Publisher

Taru Publications

Subject

General Earth and Planetary Sciences,General Environmental Science

Link

https://www.tandfonline.com/doi/pdf/10.1080/02522667.2022.2042099

Reference4 articles.

1. S. J. Saenz, J. J. Raygoza P. E. C. Becerra A. S. O. Cisneros, and J. R. Dominguez, “FPGA design and implementation of radix-2 fast Fourier transform algorithm with 16 and 32 points,” in IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC), Nov. 2015, pp. 1–6.

2. Automatic IP Generation of FFT/IFFT Processors with Word-Length Optimization for MIMO-OFDM Systems

3. DFT Computation Using Gauss-Eisenstein Basis: FFT Algorithms and VLSI Architectures

4. An algorithm for the machine calculation of complex Fourier series

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