Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers-Reference-Cited by-同舟云学术

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Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers

Published:2024-09 Issue:3 Volume:16 Page:307-310
ISSN:1943-0663
Container-title:IEEE Embedded Systems Letters
language:
Short-container-title:IEEE Embedded Syst. Lett.

Author:

Galaviz-Aguilar Jose Alejandro¹^ORCID,Vargas-Rosales Cesar¹^ORCID,Falcone Francisco¹^ORCID

Affiliation:

1. School of Engineering and Sciences, Tecnologico de Monterrey, Monterrey, Mexico

Funder

Mexico’s National Council of Science and Technology (CONACyT) under the Postdoctoral Fellowship Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/4563995/10654458/10560037.pdf?arnumber=10560037

Reference14 articles.

1. Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards

2. Design of Multiple Modulated Frequency Lock-In Amplifier for Tapping-Mode Atomic Force Microscopy Systems

3. High-Performance Digital Lock-In Amplifier Module Based on an Open-Source Red Pitaya Platform: Implementation and Applications

4. On the Accuracy of Digital Phase Sensitive Detectors Implemented in FPGA Technology

5. A Hardware-Efficient and Reconfigurable UFMC Transmitter Architecture With its FPGA Prototype

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