Systolic Digital IIR Filter Architectures for Real Time Signal Processing Applications
Author:
Affiliation:
1. Aditya Engineering College(A),Dept. of E.C.E.,Surampalem,India
2. ECE. Aditya Engineering College(A),Surampalem,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10592862/10592849/10593395.pdf?arnumber=10593395
Reference20 articles.
1. Architecture based performance evaluation of IIR digital filters for DSP applications
2. A power consumption and area improved design of IIR decimation filters via MDT
3. System generator based area reduction of IIR decimation filter;Smitha;Int J Innov Res Comput Commun Eng (IJIRCCE),2017
4. Area efficient decimation filter based on MDT for wireless applications;Rashid;The Nucleus,2013
5. Merged Delay Transformed IIR Down Sampler Filter: An efficient architecture and cost reduction technique for implementation
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