An 8.5 ps Resolution, Cyclic Vernier TDC Using a Stage-Gated Ring Oscillator and DWA-Based Dynamic Element Matching in 28 nm CMOS-Reference-Cited by-同舟云学术

An 8.5 ps Resolution, Cyclic Vernier TDC Using a Stage-Gated Ring Oscillator and DWA-Based Dynamic Element Matching in 28 nm CMOS

Published:2022 Issue: Volume:71 Page:1-12
ISSN:0018-9456
Container-title:IEEE Transactions on Instrumentation and Measurement
language:
Short-container-title:IEEE Trans. Instrum. Meas.

Author:

Nguyen Van-Nhan¹^ORCID,Pham Xuan Thanh²^ORCID,Lee Jong-Wook¹^ORCID

Affiliation:

1. Department of Electronics and Information Convergence Engineering, Information and Communication System-on-Chip (SoC) Research Center, Kyung Hee University, Yongin, Republic of Korea

2. Department of Electronics, Kyung Hee University, Yongin, Republic of Korea

Funder

Basic Science Research Program through the National Research Foundation of Korea

National Research and Development Program through the National Research Foundation of Korea funded by the Ministry of Science and Information and Communications Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Instrumentation

Link

http://xplorestaging.ieee.org/ielx7/19/9717300/09712298.pdf?arnumber=9712298

Reference35 articles.

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4. A 0.6 V 1.17 ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with $16\times$ spatial redundancy in 14 nm Fin-FET technology;kim;IEEE ISSCC Dig Tech Papers,2015

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