Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/4155018/04155026.pdf?arnumber=4155026
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1. Reconfigurable 2, 3 and 5‐point DFT processing element for SDF FFT architecture using fast cyclic convolution algorithm;Electronics Letters;2020-06
2. Hardware efficient implementation of DFT using an improved first-order moments based cyclic convolution structure;SPIE Proceedings;2015-12-14
3. Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-02
4. Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product;Advances in Intelligent Systems and Computing;2014
5. A High Performance Implementation of Non-Power-of-Two FFT with EPUMA Platform;Procedia Engineering;2012
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