Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-04960-1_28
Reference11 articles.
1. Nandi, A., Patil, S.: Performance Evaluation of One Dimensional Systolic Array for FFT Processor. In: IEEE-ICSCN, pp. 168–171 (February 2007)
2. Cheng, C., Parhi, K.K.: Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform. IEEE Transactions on Circuits and Systems-I: Regular Papers 54(4), 791–806 (2007)
3. Kung, H.T.: Why Systolic Architectures? IEEE Computer 15(1), 37–46 (1982)
4. Cooley, J.W., Tukey, J.W.: An Algorithm for the Machine Computation of Comlpex Fourier Series. Math.Comp. 19, 297–301 (1965)
5. Aravena, J.L.: Triple Matrix Product Architecture For Fast Signal Processing. IEEE Trans. Circuits Syst. 35(1), 119–122 (1988)
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