Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/4684845/04519952.pdf?arnumber=4519952
Cited by 39 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Analysis and Calibration of Bit Weights in SAR and Pipelined SAR ADCs Based on Code Distribution;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06
2. Multipurpose error calibration of pipeline analog‐to‐digital converters using decision points of the residue curve in sub‐analog‐to‐digital converters;International Journal of Circuit Theory and Applications;2024-05-24
3. A new digital background calibration technique for pipeline analog to digital converters using decision points of the voltage transfer characteristics;Analog Integrated Circuits and Signal Processing;2023-11-22
4. Transition Point Estimation Using RC-Filtered Square Wave for Calibration of SAR ADC;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-05
5. A Histogram-Based Digital Background Calibration Technique for Pipelined A/D Converters;2022 Iranian International Conference on Microelectronics (IICM);2022-12-20
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