Min-Sum Decoder Architectures With Reduced Word Length for LDPC Codes-Reference-Cited by-同舟云学术

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Min-Sum Decoder Architectures With Reduced Word Length for LDPC Codes

Published:2010-01 Issue:1 Volume:57 Page:105-115
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Daesun Oh ,Parhi K.K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/8919/5382607/04787066.pdf?arnumber=4787066

Cited by 41 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Optimized Non-Surjective FAIDs For 5G LDPC Codes With Learnable Quantization;IEEE Communications Letters;2024

2. Research on Data Link Channel Decoding Optimization Scheme for Drone Power Inspection Scenarios;Drones;2023-11-06

3. Adaptive Quantized and Normalized MSA and Its Application for DTMB-A LDPC Codes;2023 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting (BMSB);2023-06-14

4. Normalized Min-Sum Neural Network for LDPC Decoding;IEEE Transactions on Cognitive Communications and Networking;2023-02

5. Adaptive Quantized and Normalized MSA Based on Modified MET-DE and Its Application for 5G-NR LDPC Codes;IEEE Access;2023

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